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Freescale Semiconductor /MKW21Z4 /RSIM_REGS /CONTROL

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Interpret as CONTROL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BLE_RF_OSC_REQ_EN)BLE_RF_OSC_REQ_EN 0 (BLE_RF_OSC_REQ_STAT)BLE_RF_OSC_REQ_STAT 0 (BLE_RF_OSC_REQ_INT_EN)BLE_RF_OSC_REQ_INT_EN 0 (BLE_RF_OSC_REQ_INT)BLE_RF_OSC_REQ_INT 0 (0000)RF_OSC_EN 0 (RADIO_GASKET_BYPASS_OVRD_EN)RADIO_GASKET_BYPASS_OVRD_EN 0 (RADIO_GASKET_BYPASS_OVRD)RADIO_GASKET_BYPASS_OVRD 0 (IPP_OBE_3V_BLE_ACTIVE_1)IPP_OBE_3V_BLE_ACTIVE_1 0 (IPP_OBE_3V_BLE_ACTIVE_2)IPP_OBE_3V_BLE_ACTIVE_2 0 (RADIO_RAM_ACCESS_OVRD_EN)RADIO_RAM_ACCESS_OVRD_EN 0 (RADIO_RAM_ACCESS_OVRD)RADIO_RAM_ACCESS_OVRD 0 (RSIM_DSM_EXIT)RSIM_DSM_EXIT 0 (RSIM_STOP_ACK_OVRD_EN)RSIM_STOP_ACK_OVRD_EN 0 (RSIM_STOP_ACK_OVRD)RSIM_STOP_ACK_OVRD 0 (RF_OSC_READY)RF_OSC_READY 0 (RF_OSC_READY_OVRD_EN)RF_OSC_READY_OVRD_EN 0 (RF_OSC_READY_OVRD)RF_OSC_READY_OVRD 0 (BLOCK_SOC_RESETS)BLOCK_SOC_RESETS 0 (BLOCK_RADIO_OUTPUTS)BLOCK_RADIO_OUTPUTS 0 (ALLOW_DFT_RESETS)ALLOW_DFT_RESETS 0 (RADIO_RESET_BIT)RADIO_RESET_BIT

RF_OSC_EN=0000

Description

Radio System Control

Fields

BLE_RF_OSC_REQ_EN

BLE Ref Osc (Sysclk) Request Enable
BLE_RF_OSC_REQ_STAT

BLE Ref Osc (Sysclk) Request Status
BLE_RF_OSC_REQ_INT_EN

BLE Ref Osc (Sysclk) Request Interrupt Enable
BLE_RF_OSC_REQ_INT

BLE Ref Osc (Sysclk) Request Interrupt Flag
RF_OSC_EN

RF Ref Osc Enable Select

0 (0000): RF Ref Osc will be controlled by the SoC, external pin, or a link layer

1 (0001): RF Ref Osc on in Run/Wait

3 (0011): RF Ref Osc on in Stop

7 (0111): RF Ref Osc on in VLPR/VLPW

15 (1111): RF Ref Osc on in VLPS
RADIO_GASKET_BYPASS_OVRD_EN

Radio Gasket Bypass Override Enable
RADIO_GASKET_BYPASS_OVRD

Radio Gasket Bypass Override
IPP_OBE_3V_BLE_ACTIVE_1

IPP_OBE_3V_BLE_ACTIVE_1
IPP_OBE_3V_BLE_ACTIVE_2

IPP_OBE_3V_BLE_ACTIVE_2
RADIO_RAM_ACCESS_OVRD_EN

Radio RAM Access Override Enable
RADIO_RAM_ACCESS_OVRD

Radio RAM Access Override
RSIM_DSM_EXIT

BLE Force Deep Sleep Mode Exit
RSIM_STOP_ACK_OVRD_EN

Stop Acknowledge Override Enable
RSIM_STOP_ACK_OVRD

Stop Acknowledge Override
RF_OSC_READY

RF Ref Osc Ready
RF_OSC_READY_OVRD_EN

RF Ref Osc Ready Override Enable
RF_OSC_READY_OVRD

RF Ref Osc Ready Override
BLOCK_SOC_RESETS

Block SoC Resets of the Radio
BLOCK_RADIO_OUTPUTS

Block Radio Outputs
ALLOW_DFT_RESETS

Allow the DFT Reset Pin to Reset the Radio
RADIO_RESET_BIT

Software Reset for the Radio

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data